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Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
30.3
I/O Lines Description
30.4
Multiplexed Signals
Table 30-1. I/O Line Description
Name
Description
Type
Active Level
NCS[7:0]
Static Memory Controller Chip Select Lines
Output
Low
NRD
Read Signal
Output
Low
NWR0/NWE
Write 0/Write Enable Signal
Output
Low
A0/NBS0
Address Bit 0/Byte 0 Select Signal
Output
Low
NWR1/NBS1
Write 1/Byte 1 Select Signal
Output
Low
A1/NWR2/NBS2
Address Bit 1/Write 2/Byte 2 Select Signal
Output
Low
NWR3/NBS3
Write 3/Byte 3 Select Signal
Output
Low
A[25:2]
Address Bus
Output
D[31:0] Data 
Bus
I/O
NWAIT
External Wait Signal
Input
Low
Table 30-2. Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals
Related Function
NWR0
NWE
Byte-write or byte-select access, see 
A0
NBS0
8-bit or 16-/32-bit data bus, see 
NWR1
NBS1
Byte-write or byte-select access see 
A1
NWR2
NBS2
8-/16-bit or 32-bit data bus, see 
. 
Byte-write or byte-select access, see 
NWR3
NBS3
Byte-write or byte-select access see