Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of
the setup period of the next access to optimize the number of wait states cycle to insert.

 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.

Chip Select 0 has been programmed with:



NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)



NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)



TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).

NCS

TDF = 3 clock cycles

tpacc

MCK

D[31:0]

NCS controlled read operation

A[25:2]

NBS0, NBS1,
NBS2, NBS3,
A0,A1

NRD