Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the
following sequence:

1.

Program the memory device type into the Memory Device Register (see 

).

2.

Program the features of the low-power DDR1-SDRAM device into the Configuration Register: asynchronous tim-
ing (trc, tras, etc.), number of columns, rows, banks, cas latency. See 

.

3.

Program temperature compensated self refresh (tcr), Partial array self refresh (pasr) and Drive strength (ds) into 
the Low-power Register. See 

4.

An NOP command will be issued to the low-power DDR1-SDRAM. Program NOP command into the Mode Regis-
ter, the application must set Mode to 1 in the Mode Register (see 

). Perform a write 

access to any DDR1-SDRAM address to acknowledge this command. Now clocks which drive DDR1-SDRAM 
device are enabled.

A minimum pause of 200 µs will be provided to precede any signal toggle.

5.

An all banks precharge command is issued to the low-power DDR1-SDRAM. Program all banks precharge com-
mand into the Mode Register, the application must set Mode to 2 in the Mode Register (See 

). Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command

6.

Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register, 
the application must set Mode to 4 in the Mode Register (see 

). Perform a write access 

to any low-power DDR1-SDRAM location twice to acknowledge these commands.

7.

An Extended Mode Register set (EMRS) cycle is issued to program the low-power DDR1-SDRAM parameters 
(carried on TCR, PASR, DS fields in DDRSDRC_LPR register). The application must set Mode to 5 in the Mode 
Register (see 

) and perform a write access to the SDRAM to acknowledge this com-

mand.  The write address must be chosen so that BA[1] is set to 1 BA[0] is set to 0. For example, with a 16-bit 128 
MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the low-power DDR1-SDRAM write access should be 
done at address 0x20800000.

Note:

This address is for example purposes only. The real address is dependent on implementation in the product.

8.

A Mode Register set (MRS) cycle is issued to program the parameters of the low-power DDR1-SDRAM devices, in 
particular CAS latency, burst length. The application must set Mode to 3 in the Mode Register (see 

) and perform a write access to the low-power DDR1-SDRAM to acknowledge this command. The 

write address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB low-power 
DDR1-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the 
address 0x20000000. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see 

) and performing a write access at any location in the low-power DDR1-SDRAM to 

acknowledge this command.

9.

Perform a write access to any low-power DDR1-SDRAM address.

10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see 

). (Refresh rate 

= delay between refresh cycles). The low-power DDR1-SDRAM device requires a refresh every 15.625 µs or 
7.81 µs. With a 100 MHz frequency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562 
i.e. 0x061A or (7.81*100 MHz) = 781 i.e. 0x030d

11. After initialization, the low-power DDR1-SDRAM device is fully functional.