Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

DDRSDRC is partitioned in two blocks (see 

): 



An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four AHB masters and 
integrates an arbiter.



A controller that translates AHB requests (Read/Write) in the SDRAM protocol.

Memory Controller

Finite State Machine

SDRAM Signal Management

Addr, DQM

Data

Asynchronous Timing
Refresh Management

DDR-SDR

Devices

Power Management

DQS

ras,cas,we
cke

clk/nclk

odt

DDR-SDR Controller

Interconnect Matrix

Input

Stage

Input

Stage

Input

Stage

Output 

Stage

Arbiter

APB

AHB  Slave Interface 0

AHB  Slave Interface 1

AHB  Slave Interface 2

AHB  Slave Interface 3

Input

Stage

Interface  APB