Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
444
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
31.7.1  DDRSDRC Mode Register
Name:
DDRSDRC_MR
Address:
0xFFFFE800
Access:
Read-write
Reset:
See 
This register can only be written if the WPEN bit is cleared in 
• MODE: DDRSDRC Command Mode
This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to initialize 
the SDRAM device and to activate deep power-down mode.
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0
MODE
Value
Name
Description
0
NORMAL
Normal Mode. Any access to the DDRSDRC will be decoded normally. To activate this mode, 
command must be followed by a write to the SDRAM. 
1
NOP
The DDRSDRC issues a NOP command when the SDRAM device is accessed regardless 
of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
2
ALLBKPRECH
The DDRSDRC issues an “All Banks Precharge” command when the SDRAM device is 
accessed regardless of the cycle. To activate this mode, command must be followed by 
a write to the SDRAM.
3
LOADMODREG
The DDRSDRC issues a “Load Mode Register” command when the SDRAM device is 
accessed regardless of the cycle. To activate this mode, command must be followed by 
a write to the SDRAM.
4
AUTOREFRESH
The DDRSDRC issues an “Auto-Refresh” Command when the SDRAM device is accessed 
regardless of the cycle. Previously, an “All Banks Precharge” command must be issued. 
To activate this mode, command must be followed by a write to the SDRAM.
5 EXTLOADMODREG
The DDRSDRC issues an “Extended Load Mode Register” command when the SDRAM 
device is accessed regardless of the cycle. To activate this mode, the “Extended Load Mode 
Register” command must be followed by a write to the SDRAM. The write in the SDRAM must 
be done in the appropriate bank.
6
DEEPPOWER
Deep power mode: Access to deep power-down mode