Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
446
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
31.7.3 DDRSDRC Configuration Register
Name:
DDRSDRC_CR
Address:
0xFFFFE808
Access:
Read-write
Reset:
See
This register can only be written if the if the WPEN bit is cleared in
• NC: Number of Column Bits
The reset value is 9 column bits.
SDR-SDRAM devices with eight columns in 16-bit mode are not supported.
• NR: Number of Row Bits
The reset value is 12 row bits.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
DECOD
–
NB
–
ACTBST
–
EBISHARE
15
14
13
12
11
10
9
8
–
OCD
–
–
DIS_DLL
DIC
7
6
5
4
3
2
1
0
DLL
CAS
NR
NC
Value
Name
Description
0
DDR9_SDR8
9-bit for DDR, 8-bit for SDR
1
DDR10_SDR9
10-bit for DDR, 9-bit for SDR
2
DDR11_SDR10
11-bit for DDR, 10-bit for SDR
3
DDR12_SDR11
12-bit for DDR, 11-bit for SDR
Value
Name
description
0
11_BIT
11 row bit
1
12_BIT
12 row bit
2
13_BIT
13 row bit
3
14_BIT
14 row bit