Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes

AT91SAM9N12-EK

461

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

32.3

DMA Controller Peripheral Connections

The DMA Controller handles the transfer between peripherals and memory and receives triggers from the peripherals
listed in table that follows.

For each listed DMA Channel Number, the SIF and/or DIF bitfields in the DMAC_CTRLBx register must be programmed
with a value compatible to the MATRIX “Master to Slave Access” definition provided in the “Bus Matrix (MATRIX)” section
of the product datasheet. See

Section 32.8.17 ”DMAC Channel x [x = 0..7] Control B Register”

(where x is the DMA

Channel Number).

Depending on transfer descriptor location, the DSCR_IF bitfield must be programmed with a value compatible to the
MATRIX “Master to Slave Access” definition provided in the “Bus Matrix (MATRIX)” section of the product datasheet.
See

Section 32.8.15 ”DMAC Channel x [x = 0..7] Descriptor Address Register”

(where x is the DMA Channel Number).

Table 32-1. DMA Channel Definition

Instance Name

Channel T/R

DMA Channel HW Interface Number

HSMCI

RX/TX

SPI0 TX

SPI0

SPI1

USART0

USART1

USART2

USART3

TWI0

TWI1

UART0

UART1

SSC

ADC

DBGU

AES

SHA