Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
462
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.4
Block Diagram
Figure 32-1. DMA Controller (DMAC) Block Diagram
DMA Destination
DMA Channel 0
DMA Destination
Control State Machine
Destination Pointer
Management
Control State Machine
Destination Pointer
Management
DMA Source
Control State Machine
Source Pointer
Management
Control State Machine
Source Pointer
Management
DMA FIFO Controller
DMA FIFO
Up to 64 bytes
DMA Channel 0
Read data path
from source
Read data path
from source
DMA Channel 0
Write data path
to destination
Write data path
to destination
DMA Channel 1
DMA Channel 2
DMA Channel n
External
Triggers
Triggers
Soft
Triggers
Triggers
DMA
REQ/ACK
Interface
REQ/ACK
Interface
Trigger Manager
DMA Interrupt
Controller
Controller
Status
Registers
Registers
Configuration
Registers
Registers
Atmel APB rev2 Interface
DMA AHB Lite Master Interface 0
DMA AHB Lite Master Interface 1
DMA Global Control
and Data Mux
DMA Global
Request Arbiter
DMA Global Control
and Data Mux
DMA Global
Request Arbiter
DMA Destination
Requests Pool
DMA Write
Datapath Bundles
DMA Source
Requests Pool
DMA Read
Datapath Bundles
DMA
Atmel
APB
Interface
Atmel
APB
Interface
DMA Interrupt
DMA
Hardware
Handshaking
Interface
Hardware
Handshaking
Interface
AMBA AHB Layer 0
AMBA AHB Layer 1