Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
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465
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are
supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The
source and destination can independently select which method to use.
Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the 
next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer (buffer descriptor) and a 
descriptor pointer register. The DMAC fetches the LLI at the beginning of every buffer when buffer chaining is 
enabled.
Replay – The DMAC automatically reloads the channel registers at the end of each buffers to the value when the 
channel was first enabled. 
Contiguous buffers – Where the address of the next buffer is selected to be a continuation from the end of the 
previous buffer.
Picture-in-Picture Mode: DMAC contains a Picture-in-Picture mode support. When this mode is enabled, addresses are
automatically incremented by a programmable value when the DMAC channel transfer count reaches a user defined
boundary.
 illustrates a memory mapped image 4:2:2 encoded located at image_base_address in memory.
A user defined start address is defined at Picture_start_address. The incremented value is set to memory_hole_size =
image_width - picture_width, and the boundary is set to picture_width.
Figure 32-4.  Picture-In-Picture Mode Support
Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for the
master bus interface for the duration of a DMAC transfer, buffer, or chunk.
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hmastlock for the
duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel locking is asserted for the duration of bus
locking at a minimum.
DMAC PIP transfers