Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

470

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

At the end of every buffer transfer, an end of buffer interrupt is asserted if:



the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number.

Note:

The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the destination.

At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:



the channel end of the Chained Buffer Transfer Completed Interrupt is unmasked, DMAC_EBCIMR.CBTCx = ‘1’, 
when n is the channel number.

All multi-buffer transfers must end as shown in Row 1 of 

. At the end of every buffer transfer, the

DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last
buffer and the DMAC transfer is terminated. 

For rows 9, 10 and 11 of 

, (DMAC_DSCRx = 0 and DMAC_CTRLBx.AUTO is set), multi-buffer

DMAC transfers continue until the automatic mode is disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit
should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last buffer transfer.
This puts the DMAC into Row 1 state.

For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so
that LLI.DMAC_DSCRx is set to 0.

Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be
programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used.
The different transfer types are shown in 

The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx,
and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are enabled.

1.

Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status regis-
ter, DMAC_EBCISR.

3.

Program the following channel registers:

1.

Write the starting source address in the DMAC_SADDRx register for channel x.

2.

Write the starting destination address in the DMAC_DADDRx register for channel x.

3.

Write the next descriptor address in the DMA_DSCRx register for channel x with 0x0.

4.

Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1 as shown in 

. Program the DMAC_CTRLBx register with both AUTO fields set to 0.

5.

Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers 
for channel x. For example, in the register, you can program the following:

i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control

device by programming the FC of the DMAC_CTRLBx register.

ii. Set up the transfer characteristics, such as:



Transfer width for the source in the SRC_WIDTH field.



Transfer width for the destination in the DST_WIDTH field.



Source AHB Master interface layer in the SIF field where source resides.



Destination AHB Master Interface layer in the DIF field where destination resides.



Incrementing/decrementing or fixed address for source in SRC_INC field.



Incrementing/decrementing or fixed address for destination in DST_INC field.