Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
472
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
4.
Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are set as
shown in Row 4 of
shown in Row 4 of
. The LLI.DMAC_CTRLBx register of the last Linked List Item must be
shows a Linked List example with two list items.
5.
Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory (except the last) are non-zero
and point to the base address of the next Linked List Item.
and point to the base address of the next Linked List Item.
6.
Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all LLI entries in memory point
to the start source/destination buffer address preceding that LLI fetch.
to the start source/destination buffer address preceding that LLI fetch.
7.
Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLI entries
in memory are cleared.
in memory are cleared.
8.
If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx
register for channel x.
register for channel x.
9.
If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx
register for channel x.
register for channel x.
10. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the status register:
DMAC_EBCISR.
11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in
12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item.
13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The
transfer is performed.
14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx,
DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the
DMAC_DSCRx(0).
LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx,
DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the
DMAC_DSCRx(0).
15. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-
memory peripheral). The DMAC acknowledges at the completion of every transaction (chunk and single) in the
buffer and carries out the buffer transfer.
buffer and carries out the buffer transfer.
16. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to system memory at the same
location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of
the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE
bits have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buf-
fer transfer has completed.
the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE
bits have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buf-
fer transfer has completed.
Note:
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted,
then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the
transfer.
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted,
then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the
transfer.
17. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching the next LLI from the memory
location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx,
DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer
continues until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer
transfer match described in Row 1 of
DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer
continues until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer
transfer match described in Row 1 of
. The DMAC then knows that the previous buffer
transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in
.