Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
487
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.5.6 Disabling a Channel Prior to Transfer Completion
Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register,
DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx
register bit.
DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx
register bit.
The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with
the EMPTx bit in the Channel Handler Status Register.
the EMPTx bit in the Channel Handler Status Register.
1.
If the software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the
DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel
FIFO receives no new data.
DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel
FIFO receives no new data.
2.
The software can now poll the DMAC_CHSR.EMPTx bit until it indicates that the channel n FIFO is empty, where
n is the channel number.
n is the channel number.
3.
The DMAC_CHER.ENAx bit can then be cleared by software once the channel n FIFO is empty, where n is the
channel number.
channel number.
When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the DMAC_CHSRx.SUSPx bit is
high, the DMAC_CHSRx.EMPTx is asserted once the contents of the FIFO does not permit a single word of
DMAC_CTRLAx.DST_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form
a single transfer of DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remaining
data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the
suspension state by writing a ‘1’ to the DMAC_CHER.RESx field register. The DMAC transfer completes in the normal
manner. n defines the channel number.
high, the DMAC_CHSRx.EMPTx is asserted once the contents of the FIFO does not permit a single word of
DMAC_CTRLAx.DST_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form
a single transfer of DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remaining
data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the
suspension state by writing a ‘1’ to the DMAC_CHER.RESx field register. The DMAC transfer completes in the normal
manner. n defines the channel number.
Note:
If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an
acknowledgement.
acknowledgement.
32.5.6.1 Abnormal Transfer Termination
A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit, DMAC_CHDR.ENAx,
where x is the channel number. This does not mean that the channel is disabled immediately after the
DMAC_CHSR.ENAx bit is cleared over the APB interface. Consider this as a request to disable the channel. The
DMAC_CHSR.ENAx must be polled and then it must be confirmed that the channel is disabled by reading back 0.
where x is the channel number. This does not mean that the channel is disabled immediately after the
DMAC_CHSR.ENAx bit is cleared over the APB interface. Consider this as a request to disable the channel. The
DMAC_CHSR.ENAx must be polled and then it must be confirmed that the channel is disabled by reading back 0.
The software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register
(DMAC_EN.ENABLE bit). Again, this does not mean that all channels are disabled immediately after the
DMAC_EN.ENABLE is cleared over the APB slave interface. Consider this as a request to disable all channels. The
DMAC_CHSR.ENABLE must be polled and then it must be confirmed that all channels are disabled by reading back ‘0’.
(DMAC_EN.ENABLE bit). Again, this does not mean that all channels are disabled immediately after the
DMAC_EN.ENABLE is cleared over the APB slave interface. Consider this as a request to disable all channels. The
DMAC_CHSR.ENABLE must be polled and then it must be confirmed that all channels are disabled by reading back ‘0’.
Note:
If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination
peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals, such as a
source FIFO, this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling
a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the
source peripheral upon request and is not lost.
peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals, such as a
source FIFO, this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling
a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the
source peripheral upon request and is not lost.
Note:
If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an
acknowledgement.
acknowledgement.