Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

–Both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).

–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able 

to prefetch data and write HSMCI simultaneously.

8.

Configure the fields of LLI(n).DMAC_CFGx for Channel x as follows:

–FIFOCFG defines the watermark of the DMA channel FIFO.

–DST_H2SEL is set to true to enable hardware handshaking on the destination.

–SRC_REP is set to 0. (contiguous memory access at block boundary)

–DST_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host 

Controller.

9.

If LLI(n) is the last descriptor, then LLI(n).DSCR points to 0 else LLI(n) points to the start address of 
LLI(n+1).

10. Program DMAC_CTRLBx for the Channel Register x with 0. Its content is updated with the LLI fetch 

operation.

11. Program DMAC_DSCRx register for the Channel Register x with the address of the first descriptor LLI(0).

12. Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting for request.

7.

Poll CBTC[x] bit in the DMAC_EBCISR.

8.

If a new list of buffers shall be transferred, repeat step 6. Check and handle HSMCI errors.

9.

Poll FIFOEMPTY field in the HSMCI_SR.

10. Send The STOP_TRANSMISSION command writing HSMCI_ARG then HSMCI_CMDR.

11. Wait for XFRDONE in the HSMCI_SR.

1.

Wait until the current command execution has successfully terminated.

1.

Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.

2.

Program the block length in the card. This value defines the value block_length.

3.

Program the block length in the HSMCI Configuration Register with block_length value.

4.

Set RDPROOF bit in HSMCI_MR to avoid overflow.

5.

Configure the fields of the HSMCI_DMA register as follows:



ROPT field is set to 0.



OFFSET field is set to 0.



CHKSIZE is user defined.



DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to 
false.

6.

Issue a READ_MULTIPLE_BLOCK command.

7.

Program the DMA Controller to use a list of descriptors:

1.

Read the channel register to choose an available (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMA transfer by reading the 
DMAC_EBCISR.

3.

Program the channel registers in the Memory with the first descriptor. This descriptor will be word oriented. 
This descriptor is referred to as LLI_W(n), standing for LLI word oriented transfer for block n.

4.

The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO 
address.

5.

The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.