Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
581
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
6.
Configure the fields of LLI_W(n).DMAC_CTRLAx as follows:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
7.
Configure the fields of LLI_W(n).DMAC_CTRLBx as follows:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
–DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is
able to prefetch data and write HSMCI simultaneously.
8.
Configure the fields of the LLI_W(n).DMAC_CFGx register for Channel x as follows:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Addresses are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
9.
Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the
AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then
LLI_W(n).DMAC_DSCRx points to 0.
AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then
LLI_W(n).DMAC_DSCRx points to 0.
10. Program the DMAC_CTRLBx register for Channel x with 0. Its content is updated with the LLI Fetch
operation.
11. Program DMAC_DSCRx register for Channel x with the address of LLI_W(0).
12. Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting for request.
8.
Poll CBTC[x] bit in the DMAC_EBCISR.
9.
If a new list of buffer shall be transferred repeat step 6. Check and handle HSMCI errors.
10. Poll FIFOEMPTY field in the HSMCI_SR.
11. Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the HSMCI_CMDR.
12. Wait for XFRDONE in the HSMCI_SR.
35.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)
Two DMA Transfer descriptors are used to perform the HSMCI block transfer.
1.
Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK command.
2.
Issue a READ_MULTIPLE_BLOCK command.
3.
Program the DMA Controller to use a list of descriptors.
1.
Read the channel register to choose an available (disabled) channel.
2.
Clear any pending interrupts on the channel from the previous DMAC transfer by reading the
DMAC_EBCISR.
DMAC_EBCISR.
3.
For every block of data repeat the following procedure:
4.
Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented.
This descriptor is referred to as LLI_W(n) standing for LLI word oriented transfer for block n.
This descriptor is referred to as LLI_W(n) standing for LLI word oriented transfer for block n.
5.
The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO
address.
address.