Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
642
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
36.8.9 SPI Chip Select Register
Name: SPI_CSRx[x=0..3]
Addresses:
0xF0000030 (0), 0xF0004030 (1)
Access:
Read/Write
This register can only be written if the WPEN bit is cleared in
Note:
SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with
the translated value unless the register is written.
the translated value unless the register is written.
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
with CPOL to produce the required clock/data relationship between master and slave devices.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0 = The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer
and if the two transfers occur on the same Chip Select.
and if the two transfers occur on the same Chip Select.
1 = The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after the
end of transfer for a minimal duration of:
end of transfer for a minimal duration of:
–
(if DLYBCT field is different from 0)
–
(if DLYBCT field equals 0)
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
on a different chip select.
• BITS: Bits Per Transfer
(See the
31
30
29
28
27
26
25
24
DLYBCT
23
22
21
20
19
18
17
16
DLYBS
15
14
13
12
11
10
9
8
SCBR
7
6
5
4
3
2
1
0
BITS
CSAAT
CSNAAT
NCPHA
CPOL
DLYBCT
MCK
-----------------------
DLYBCT
1
+
MCK
---------------------------------