Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

643

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The BITS field determines the number of data bits transferred. Reserved values should not be used.

In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud 
rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:

Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. 

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

Note:

If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they 
are required to process transfers. If they are not used to transfer data, they can be set at any value.

This field defines the delay from NPCS valid to the first valid SPCK transition. 

When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.

Otherwise, the following equations determine the delay:

This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The 
delay is always inserted after each transfer and before removing the chip select if needed.

When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the char-
acter transfers.

Otherwise, the following equation determines the delay:

0

8_BIT

8 bits for transfer

1

9_BIT

9 bits for transfer

2

10_BIT

10 bits for transfer

3

11_BIT

11 bits for transfer

4

12_BIT

12 bits for transfer

5

13_BIT

13 bits for transfer

6

14_BIT

14 bits for transfer

7

15_BIT

15 bits for transfer

8

16_BIT

16 bits for transfer

9

–

Reserved

10

–

Reserved

11

–

Reserved

12

–

Reserved

13

–

Reserved

14

–

Reserved

15

–

Reserved

 SPCK Baudrate

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=

Delay Before SPCK

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=

Delay Between Consecutive Transfers

32

×

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=