Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the
nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this
mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the
processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle
an interrupt. It is strongly recommended to use this mask with caution.

To prevent any single software error that may corrupt AIC behavior, the registers listed below can be write-protected by
setting the WPEN bit in the 

 (AIC_WPMR). 

If a write access in a write-protected register is detected, then the WPVS flag in the 

(AIC_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted. 

The WPVS flag is automatically reset after reading the AIC Write Protect Status Register.

The protected registers are:

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