Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
686
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies
that after reset clkA (clkB) are turned off.
that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the
PWM master clock is turned off through the Power Management Controller.
PWM master clock is turned off through the Power Management Controller.
38.6.2 PWM
Channel
38.6.2.1 Block Diagram
Figure 38-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of three blocks:
A clock selector which selects one of the clocks provided by the clock generator described in
An internal counter clocked by the output of the clock selector. This internal counter is incremented or
decremented according to the channel configuration and comparators events. The size of the internal counter is 32
bits.
decremented according to the channel configuration and comparators events. The size of the internal counter is 32
bits.
A comparator used to generate events according to the internal counter value. It also computes the PWMx output
waveform according to the configuration.
waveform according to the configuration.
38.6.2.2 Waveform Properties
The different properties of output waveforms are:
the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock
generator described in the previous section. This channel parameter is defined in the CPRE field of the
PWM_CMRx register. This field is reset at 0.
generator described in the previous section. This channel parameter is defined in the CPRE field of the
PWM_CMRx register. This field is reset at 0.
the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be
calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
- If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be
calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
If the waveform is center aligned then the output waveform period depends on the counter source clock and can
be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
Comparator
PWMx
output waveform
output waveform
Internal
Counter
Clock
Selector
Inputs
from clock
generator
Inputs from
APB bus
Channel
X
CPRD
×
(
)
MCK
-------------------------------
X
*
CPRD
*
DIVA
(
)
MCK
----------------------------------------------
X
*
CPRD
*
DIVB
(
)
MCK
----------------------------------------------
2
X
CPRD
×
×
(
)
MCK
-----------------------------------------