Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
687
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is left aligned then:
If the waveform is center aligned, then:
the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is
defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be
used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx
register. The default mode is left aligned.
used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx
register. The default mode is left aligned.
Figure 38-4. Non Overlapped Center Aligned Waveforms
Note:
1.
See
for a detailed description of center aligned waveforms.
When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period.
When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.
Waveforms are fixed at 0 when:
CDTY = CPRD and CPOL = 0
CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
CDTY = 0 and CPOL = 0
CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level.
Changes on channel polarity are not taken into account while the channel is enabled.
Changes on channel polarity are not taken into account while the channel is enabled.
2*
X
*
CPRD
*
DIVA
(
)
MCK
----------------------------------------------------
2*
X
*
CPRD
*
DIVB
(
)
MCK
----------------------------------------------------
duty cycle
period
1 fchannel_x_clock
CDTY
×
⁄
–
(
)
period
--------------------------------------------------------------------------------------------------------
=
duty cycle
period
2
⁄
(
)
1 fchannel_x_clock
CDTY
×
⁄
–
(
) )
period
2
⁄
(
)
-----------------------------------------------------------------------------------------------------------------------
=
PWM0
PWM1
Period
No overlap