Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
689
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
38.6.3 PWM
Controller
Operations
38.6.3.1 Initialization
Before enabling the output channel, this channel must have been configured by the software application:
Configuration of the clock generator if DIVA and DIVB are required
Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx
Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx
Register to update PWM_CPRDx as explained below.
Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx
Register to update PWM_CPRDx as explained below.
Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx
Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx
Register to update PWM_CDTYx as explained below.
Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx
Register to update PWM_CDTYx as explained below.
Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)
Enable Interrupts (Writing CHIDx in the PWM_IER register)
Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously
several CHIDx bits in the PWM_ENA register.
several CHIDx bits in the PWM_ENA register.
In such a situation, all channels may have the same clock selector configuration and the same period specified.
38.6.3.2 Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the value in the Period Register
(PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in
the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The
higher the value of PWM_CPRDx, the greater the PWM accuracy.
(PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in
the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The
higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in
PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.
PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.
38.6.3.3 Changing the Duty Cycle or the Period
It is possible to modulate the output waveform duty cycle or period.
To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change waveform
parameters while the channel is still enabled. The user can write a new period value or duty cycle value in the update
register (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the
next cycle. Depending on the CPD field in the PWM_CMRx register, PWM_CUPDx either updates PWM_CPRDx or
PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than the duty cycle.
parameters while the channel is still enabled. The user can write a new period value or duty cycle value in the update
register (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the
next cycle. Depending on the CPD field in the PWM_CMRx register, PWM_CUPDx either updates PWM_CPRDx or
PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than the duty cycle.