Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

700

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

PWM_CMR[0..3]

0xF8034200 [0], 0xF8034220 [1], 0xF8034240 [2], 0xF8034260 [3]

Read/Write 

Values which are not listed in the table must be considered as “reserved”.

0 = The period is left aligned.

1 = The period is center aligned.

0 = The output waveform starts at a low level.

1 = The output waveform starts at a high level.

0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.

1 = Writing to the PWM_CUPDx will modify the period at the next period start event.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

–

CPD

CPOL

CALG

7

6

5

4

3

2

1

0

–

–

–

–

CPRE

0000

MCK 

Master Clock

0001

MCKDIV2

Master Clock divided by 2

0010

MCKDIV4

Master Clock divided by 4

0011

MCKDIV8

Master Clock divided by 8

0100

MCKDIV16

Master Clock divided by 16

0101

MCKDIV32

Master Clock divided by 32

0110

MCKDIV64

Master Clock divided by 64

0111

MCKDIV128

Master Clock divided by 128

1000

MCKDIV256

Master Clock divided by 256

1001

MCKDIV512

Master Clock divided by 512

1010

MCKDIV1024

Master Clock divided by 1024

1011

CLKA

Clock A

1100

CLKB

Clock B