Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
701
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
38.7.10 PWM Channel Duty Cycle Register
Name:
PWM_CDTY[0..3]
Address:
0xF8034204 [0], 0xF8034224 [1], 0xF8034244 [2], 0xF8034264 [3]
Access:
Read/Write
Only the first 32 bits (internal channel counter size) are significant.
• CDTY: Channel Duty Cycle
Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
31
30
29
28
27
26
25
24
CDTY
23
22
21
20
19
18
17
16
CDTY
15
14
13
12
11
10
9
8
CDTY
7
6
5
4
3
2
1
0
CDTY