Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

837

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

US_LINMR

0xF801C054 (0), 0xF8020054 (1), 0xF8024054 (2), 0xF8028054 (3)

Read-write 

This register is relevant only if USART_MODE = 0xA or 0xB in 

This register can only be written if the WPEN bit is cleared in 

Values which are not listed in the table must be considered as “reserved”.

0: In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node configu-
ration, the parity is checked automatically.

1: Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked.

0: In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the checksum is 
checked automatically.

1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked.

0: LIN 2.0 “Enhanced” Checksum

1: LIN 1.3 “Classic” Checksum

0: The response data length is defined by the field DLC of this register.

1: The response data length is defined by the bits 5 and 6 of the Identifier (IDCHR in US_LINIR).

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

PDCM

15

14

13

12

11

10

9

8

DLC

7

6

5

4

3

2

1

0

WKUPTYP

FSDIS

DLM

CHKTYP

CHKDIS

PARDIS

NACT

00

PUBLISH

The USART transmits the response.

01

SUBSCRIBE

The USART receives the response.

10

IGNORE

The USART does not transmit and does not receive the response.