Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O
pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can
be inverted independently by the CKI bits in SSC_RCMR. 

The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is
configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO
field) can lead to unpredictable results.

The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK
pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on
the RK pin is:



Master Clock divided by 2 if Receiver Frame Synchro is input



Master Clock divided by 3 if Receiver Frame Synchro is output

In addition, the maximum clock speed allowed on the TK pin is:



Master Clock divided by 6 if Transmit Frame Synchro is input



Master Clock divided by 2 if Transmit Frame Synchro is output

RK (pin)

Receiver
Clock

Divider

Clock

MUX

Tri_state

Controller

Clock 
Output

CKO

Data Transfer

CKS

INV

MUX

Tri_state

Controller

Transmitter

Clock

CKI

CKG