Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
969
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.7
LCD Controller (LCDC) User Interface
Table 44-32. Register Mapping
Offset
Register
Name
Access
Reset
0x00000000
LCD Controller Configuration Register 0
LCDC_LCDCFG0
Read-write
0x00000000
0x00000004
LCD Controller Configuration Register 1
LCDC_LCDCFG1
Read-write
0x00000000
0x00000008
LCD Controller Configuration Register 2
LCDC_LCDCFG2
Read-write
0x00000000
0x0000000C
LCD Controller Configuration Register 3
LCDC_LCDCFG3
Read-write
0x00000000
0x00000010
LCD Controller Configuration Register 4
LCDC_LCDCFG4
Read-write
0x00000000
0x00000014
LCD Controller Configuration Register 5
LCDC_LCDCFG5
Read-write
0x00000000
0x00000018
LCD Controller Configuration Register 6
LCDC_LCDCFG6
Read-write
0x00000000
0x0000001C
Reserved
–
–
–
0x00000020
LCD Controller Enable Register
LCDC_LCDEN
Write-only
–
0x00000024
LCD Controller Disable Register
LCDC_LCDDIS
Write-only
–
0x00000028
LCD Controller Status Register
LCDC_LCDSR
Read-only
0x00000000
0x0000002C
LCD Controller Interrupt Enable Register
LCDC_LCDIER
Write-only
-
0x00000030
LCD Controller Interrupt Disable Register
LCDC_LCDIDR
Write-only
-
0x00000034
LCD Controller Interrupt Mask Register
LCDC_LCDIMR
Read-only
0x00000000
0x00000038
LCD Controller Interrupt Status Register
LCDC_LCDISR
Read-only
0x00000000
0x0000003C
Reserved
–
–
–
0x00000040
Base Layer Channel Enable Register
LCDC_BASECHER
Write-only
0x00000000
0x00000044
Base Layer Channel Disable Register
LCDC_BASECHDR
Write-only
0x00000000
0x00000048
Base Layer Channel Status Register
LCDC_BASECHSR
Read-only
0x00000000
0x0000004C
Base Layer Interrupt Enable Register
LCDC_BASEIER
Write-only
0x00000000
0x00000050
Base Layer Interrupt Disabled Register
LCDC_BASEIDR
Write-only
0x00000000
0x00000054
Base Layer Interrupt Mask Register
LCDC_BASEIMR
Read-only
0x00000000
0x00000058
Base Layer Interrupt status Register
LCDC_BASEISR
Read-only
0x00000000
0x0000005C
Base Layer DMA Head Register
LCDC_BASEHEAD
Read-write
0x00000000
0x00000060
Base Layer DMA Address Register
LCDC_BASEADDR
Read-write
0x00000000
0x00000064
Base Layer DMA Control Register
LCDC_BASECTRL
Read-write
0x00000000
0x00000068
Base Layer DMA Next Register
LCDC_BASENEXT
Read-write
0x00000000
0x0000006C
Base Layer Configuration Register 0
LCDC_BASECFG0
Read-write
0x00000000
0x00000070
Base Layer Configuration Register 1
LCDC_BASECFG1
Read-write
0x00000000
0x00000074
Base Layer Configuration Register 2
LCDC_BASECFG2
Read-write
0x00000000
0x00000078
Base Layer Configuration Register 3
LCDC_BASECFG3
Read-write
0x00000000
0x0000007C
Base Layer Configuration Register 4
LCDC_BASECFG4
Read-write
0x00000000
0x80-0x3FC
Reserved
–
–
–
0x400
Base CLUT Register 0
LCDC_BASECLUT0
Read-write
0x00000000
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