Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
971
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.7.1 LCD Controller Configuration Register 0
Name:
LCDC_LCDCFG0
Address:
0xF8038000
Access:
Read-write
Reset:
0x00000000
• CLKPOL: LCD Controller Clock Polarity
0: Data/Control signals are launched on the rising edge of the Pixel Clock.
1: Data/Control signals are launched on the falling edge of the Pixel Clock.
• CLKSEL: LCD Controller Clock Source Selection
0: The Asynchronous output stage of the LCD controller is fed by MCK.
1: The Asynchronous output state of the LCD controller is fed by 2x MCK.
• CLKPWMSEL: LCD Controller PWM Clock Source Selection
0: The slow clock is selected and feeds the PWM module.
1: The system clock is selected and feeds the PWM module.
• CGDISBASE: Clock Gating Disable Control for the Base Layer
0: Automatic Clock Gating is enabled for the Base Layer.
1: Clock is running continuously.
• CLKDIV: LCD Controller Clock Divider
8 bit width clock divider for pixel clock LCD_PCLK.
pixel_clock = selected_clock/(CLKDIV+2)
where selected_clock is equal to system_clock when CLKSEL field is set to 0 and system_clock2x when CLKSEL is set to one.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
CLKDIV
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
CGDISBASE
7
6
5
4
3
2
1
0
–
–
–
–
CLKPWMSEL
CLKSEL
–
CLKPOL