Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
979
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.7.8  LCD Controller Enable Register
Name: 
LCDC_LCDEN
Address:
0xF8038020
Access: 
Write
Reset: 
0x00000000
• CLKEN: LCD Controller Pixel Clock Enable
0: Writing this field to zero has no effect.
1: When set to one the pixel clock logical unit is activated.
• SYNCEN: LCD Controller Horizontal and Vertical Synchronization Enable
0: Writing this field to zero has no effect.
1: When set to one, both horizontal and vertical synchronization (LCD_VSYNC and LCD_HSYNC) signals are generated.
• DISPEN: LCD Controller DISP Signal Enable
0: Writing this field to zero has no effect.
1: When set to one, LCD_DISP signals is generated.
• PWMEN: LCD Controller Pulse Width Modulation Enable
0: Writing this field to zero has no effect.
1: When set to one, the PWM is enabled.
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PWMEN
DISPEN
SYNCEN
CLKEN