Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
980
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.7.9 LCD
Controller Disable Register
Name:
LCDC_LCDDIS
Address:
0xF8038024
Access:
Write
Reset:
0x00000000
• CLKDIS: LCD Controller Pixel Clock Disable
0: No effect.
1: Disable the pixel clock.
• SYNCDIS: LCD Controller Horizontal and Vertical Synchronization Disable
0: No effect.
1: Disable the synchronization signals after the end of the frame.
• DISPDIS: LCD Controller DISP Signal Disable
0: No effect.
1: Disable the DISP signal.
• PWMDIS: LCD Controller Pulse Width Modulation Disable
0: No effect.
1: Disable the pulse width modulation signal.
• CLKRST: LCD Controller Clock Reset
0: No effect.
1: Reset the pixel clock generator module. The pixel clock duty cycle may be violated.
• SYNCRST: LCD Controller Horizontal and Vertical Synchronization Reset
0: No effect.
1: Reset the timing engine. Both Horizontal and vertical pulse width are violated.
• DISPRST: LCD Controller DISP Signal Reset
0: No effect.
1: Reset the DISP signal.
• PWMRST: LCD Controller PWM Reset
0: No effect.
1: Reset the PWM module, the duty cycle may be violated.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PWMRST
DISPRST
SYNCRST
CLKRST
7
6
5
4
3
2
1
0
–
–
–
–
PWMDIS
DISPDIS
SYNCDIS
CLKDIS