Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
591
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
35.14.2 HSMCI Mode Register
Name: HSMCI_MR
Address:
0xF0008004
Access: Read/Write
This register can only be written if the WPEN bit is cleared in
.
• CLKDIV: Clock Divider
High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by ({CLKDIV,CLKODD}+2).
• PWSDIV: Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2
(PWSDIV)
+ 1 when entering Power Saving Mode.
Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN bit).
• RDPROOF: Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data integ-
rity, not bandwidth.
rity, not bandwidth.
0: Disables Read Proof.
1: Enables Read Proof.
• WRPROOF: Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data integ-
rity, not bandwidth.
rity, not bandwidth.
0: Disables Write Proof.
1: Enables Write Proof.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported.
Warning: BLKLEN value depends on FBYTE.
0: Disables Force Byte Transfer.
1: Enables Force Byte Transfer.
• PADV: Padding Value
0: 0x00 value is used when padding data in write transfer.
1: 0xFF value is used when padding data in write transfer.
PADV may be only in manual transfer.
• CLKODD: Clock divider is odd
This bit is the least significant bit of the clock divider and indicates the clock divider parity.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
CLKODD
15
14
13
12
11
10
9
8
–
PADV
FBYTE
WRPROOF
RDPROOF
PWSDIV
7
6
5
4
3
2
1
0
CLKDIV