Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

109

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

The User Reset is entered when a low level is detected on the NRST pin  When a falling edge occurs on NRST (reset 
activation), internal reset lines are immediately asserted.

The Processor Reset and the Peripheral Reset are asserted. 

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The 
processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the 
value 0x4, indicating a User Reset.

The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as 
programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is 
driven low externally, the internal reset lines remain asserted until NRST actually rises. 

SLCK

periph_nreset

proc_nreset

Main Supply

POR output

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 4 cycles (ERSTL = 1)

MCK

Processor Startup 

backup_nreset

Any

Freq.

Resynch.

2 cycles

RSTTYP

XXX

0x1 = WakeUp Reset

XXX