Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
110
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 14-6. User Reset State
14.4.4.4 Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These commands are
performed by writing the Control Register (RSTC_CR) with the following bits at 1:
performed by writing the Control Register (RSTC_CR) with the following bits at 1:
PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in
particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously.)
particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously.)
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode
Register (RSTC_MR).
Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be performed
independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock
(MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
(MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the
resulting falling edge on NRST does not lead to a User Reset.
resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status
Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status
Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while
the SRCMP bit is set, and writing any value in RSTC_CR has no effect.
Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while
the SRCMP bit is set, and writing any value in RSTC_CR has no effect.
SLCK
periph_nreset
proc_nreset
NRST
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
MCK
Processor Startup
Any
Freq.
RSTTYP
Any
XXX
Resynch.
2 cycles
0x4 = User Reset