Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

111

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3

 

Slow Clock cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:



If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, 
depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a 
User Reset state.



If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if 
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default 
and with a period set to a maximum.

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. 

SLCK

periph_nreset

if PERRST=1

proc_nreset

if PROCRST=1

Write RSTC_CR

NRST

(nrst_out)

if EXTRST=1

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup 

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x3 = Software Reset

Resynch.

1 to 2 cycles

SRCMP in RSTC_SR