Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
822
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 39-38.SPI Transfer Format (CPHA=0, 8 bits per transfer)
39.7.7.4 Receiver and Transmitter Control
39.7.7.5 Character Transmission
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in
the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and
TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character
processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY rises.
the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and
TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character
processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY
is low has no effect and the written character is lost.
is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (US_THR) is
empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE
bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE
bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit (Time bit) before the transmission of the
MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always
released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to
address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can
be forced at low level by writing the Control Register (US_CR) with the RTSEN bit to 1. The slave select line (NSS) can
be released at high level only by writing the Control Register (US_CR) with the RTSDIS bit to 1 (for example, when all
data have been transferred to the slave device).
MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always
released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to
address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can
be forced at low level by writing the Control Register (US_CR) with the RTSEN bit to 1. The slave select line (NSS) can
be released at high level only by writing the Control Register (US_CR) with the RTSDIS bit to 1 (for example, when all
data have been transferred to the slave device).
In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character
transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit
before the first serial clock cycle corresponding to the MSB bit.
transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit
before the first serial clock cycle corresponding to the MSB bit.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
1
2
3
4
5
7
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
2
2
6