Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
1010
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
43.7.3.1
AC97 Controller Setup
The following operations must be performed in order to bring the AC97 Controller into an operating state:
1.
Enable the AC97 Controller clock in the PMC controller.
2.
Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register (AC97C_MR).
3.
Configure the input channel assignment by controlling the AC97 Controller Input Assignment Register
(AC97C_ICA).
(AC97C_ICA).
4.
Configure the output channel assignment by controlling the AC97 Controller Input Assignment Register
(AC97C_OCA).
(AC97C_OCA).
5.
Configure sample width for Channel A, Channel Bby writing the SIZE bit field in AC97C Channel x Mode
Register (AC97C_CAMR), (AC97C_CBMR). The application can write 10, 16, 18,or 20-bit wide PCM
samples through the AC97 interface and they will be transferred into 20-bit wide slots.
Register (AC97C_CAMR), (AC97C_CBMR). The application can write 10, 16, 18,or 20-bit wide PCM
samples through the AC97 interface and they will be transferred into 20-bit wide slots.
6.
Configure data Endianness for Channel A, Channel B by writing CEM bit field in (AC97C_CAMR),
(AC97C_CBMR) register. Data on the AC-link are shifted MSB first. The application can write little- or big-
endian data to the AC97 Controller interface.
(AC97C_CBMR) register. Data on the AC-link are shifted MSB first. The application can write little- or big-
endian data to the AC97 Controller interface.
7.
Configure the PIO controller to drive the RESET signal of the external Codec. The RESET signal must ful-
fill external AC97 Codec timing requirements.
fill external AC97 Codec timing requirements.
8.
Enable Channel A and/or Channel B by writing CEN bit field in AC97C_CxMR register.
43.7.3.2
Transmit Operation
The application must perform the following steps in order to send data via a channel to the AC97 Codec:
• Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status Register
(AC97_CxSR). x being one of the 2 channels.
• Write data to the AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically set by the AC97
Controller which allows the application to start a new write action. The application can also wait for an interrupt
notice associated with TXRDY in order to send data. The interrupt remains active until TXRDY flag is cleared.
Controller which allows the application to start a new write action. The application can also wait for an interrupt
notice associated with TXRDY in order to send data. The interrupt remains active until TXRDY flag is cleared.
Figure 43-5.
Audio Transfer (PCM L Front, PCM R Front) on Channel x
The TXEMPTY flag in the AC97 Controller Channel x Status Register (AC97C_CxSR) is set when all requested
transmissions for a channel have been shifted on the AC-link. The application can either poll TXEMPTY flag in
AC97C_CxSR or wait for an interrupt notice associated with the same flag.
transmissions for a channel have been shifted on the AC-link. The application can either poll TXEMPTY flag in
AC97C_CxSR or wait for an interrupt notice associated with the same flag.
Slot #
AC97FS
TAG
CMD
ADDR
CMD
DATA
0
AC97TX
(Controller Output)
PCM
L Front
PCM
R Front
LINE 1
DAC
PCM
Center
PCM
L SURR
PCM
R SURR
PCM
LFE
LINE 2
DAC
HSET
DAC
IO
CTRL
1
2
3
4
5
6
7
8
9
10
11
12
TXRDYCx
(AC97C_SR)
Write access to
AC97C_THRx
PCM L Front
transfered to the shift register
PCM R Front
transfered to the shift register
TXEMPTY
(AC97C_SR)