Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
1057
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
45.6.2.7
Shifter
The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome mode and three
sub-pixels at a time in color mode (R,G,B components). This module packs the data according to the output inter-
face. This interface can be programmed in the DISTYPE, SCANMOD, and IFWIDTH fields of the LDCCON3
register.
sub-pixels at a time in color mode (R,G,B components). This module packs the data according to the output inter-
face. This interface can be programmed in the DISTYPE, SCANMOD, and IFWIDTH fields of the LDCCON3
register.
The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCANMODE field selects
between single and dual scan modes; in TFT mode, only single scan is supported. The IFWIDTH field configures
the width of the interface in STN mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only).
between single and dual scan modes; in TFT mode, only single scan is supported. The IFWIDTH field configures
the width of the interface in STN mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only).
For a more detailed description of the fields, see
.
For a more detailed description of the LCD Interface, see
45.6.2.8
Timegen
The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC, LCDDEN, and
LCDMOD, used by the LCD module. This block is programmable in order to support different types of LCD mod-
ules and obtain the output clock signals, which are derived from the LCDC Core clock.
LCDMOD, used by the LCD module. This block is programmable in order to support different types of LCD mod-
ules and obtain the output clock signals, which are derived from the LCDC Core clock.
The LCDMOD signal provides an AC signal for the display. It is used by the LCD to alternate the polarity of the row
and column voltages used to turn the pixels on and off. This prevents the liquid crystal from degradation. It can be
configured to toggle every frame (bit MMODE = 0 in LCDMVAL register) or to toggle every programmable number
of LCDHSYNC pulses (bit MMODE = 1, number of pulses defined in MVAL field of LCDMVAL register).
and column voltages used to turn the pixels on and off. This prevents the liquid crystal from degradation. It can be
configured to toggle every frame (bit MMODE = 0 in LCDMVAL register) or to toggle every programmable number
of LCDHSYNC pulses (bit MMODE = 1, number of pulses defined in MVAL field of LCDMVAL register).
show the timing of LCDMOD in both configurations.
Figure 45-3.
Full Frame Timing, MMODE=1, MVAL=1
Figure 45-4.
Full Frame Timing, MMODE=0
The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is sent through
LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL
field of LCDCON1 register controls the rate of this signal. The divisor can also be bypassed with the BYPASS bit in
the LCDCON1 register. In this case, the rate of LCDDOTCK is equal to the frequency of the LCDC Core clock. The
LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL
field of LCDCON1 register controls the rate of this signal. The divisor can also be bypassed with the BYPASS bit in
the LCDCON1 register. In this case, the rate of LCDDOTCK is equal to the frequency of the LCDC Core clock. The
f
LCD_MOD
f
LCD_HSYNC
2
MVAL
1
+
(
)
×
----------------------------------------
=
LCDVSYNC
LCDMOD
LCDDOTCK
Line1
Line2
Line3
Line4
Line5
LCDVSYNC
LCDMOD
LCDDOTCK
Line1
Line2
Line3
Line4
Line5