Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

Product codes

AT91SAM9M10-G45-EK

1059

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

45.6.2.9

Equation 1

where:

• VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers

• PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles

• DPATH_LATENCY is the datapath latency of the configuration, given in

Table 45-4 on page 1051

The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line pointer to start over at
the top of the display. The timing of this signal depends on the type of LCD: STN or TFT LCD.

In STN mode, the high phase corresponds to the complete first line of the frame. In STN mode, this signal is syn-
chronized with the first active LCDDOTCK rising edge in a line.

In TFT mode, the high phase of this signal starts at the beginning of the first line. The following timing parameters
can be selected:

• Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the LCDTIM1 register. The

pulse width is equal to (VPW+1) lines.

• Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in VBP field of

LCDTIM1 register. The number of inactive lines is equal to VBP. This field should be programmed with 0 in STN
Mode.

• Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP field of LCDTIM2

There are two other parameters to configure in this module, the HOZVAL and the LINEVAL fields of the
LCDFRMCFG:

• HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of active cycles in each

line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1.

• LINEVAL configures the number of active lines per frame. This number is equal to (LINEVAL+1) lines. The

minimum value of this parameter is 1.

show the timing of LCDDOTCK, LCDDEN, LCDHSYNC and LCDVSYNC

signals:

VHDLY

HPW

HBP

(

) PCLK_PERIOD

DPATH_LATENCY

≥