Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 1069

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

– LCDFIFO register: To program it, use the formula in section 

– LCDMVAL register: Its configuration depends on the LCD Module used and should be tuned to improve 

the image quality in the display (

– DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the dithering patterns 

used to generate gray shades or colors in these modules. They are loaded with recommended patterns 
at reset, so it is not necessary to write anything on them. They can be used to improve the image 
quality in the display by tuning the patterns in each application.

– PWRCON Register: this register controls the power-up sequence of the LCD, so take care to use it 

properly. Do not enable the LCD (writing a 1 in LCD_PWR field) until the previous steps and the 
configuration of the DMA have been finished. 

– CONTRAST_CTR and CONTRAST_VAL: use this registers to adjust the contrast of the display, when 

the LCDCC line is used. 

• Configure the DMA Controller. The user should configure the base address of the display buffer memory, the 

size of the AHB transaction and the size of the display image in memory. When the DMA is configured the user 
should enable the DMA. To do so the user should configure the following registers:

– DMABADDR1 and DMABADDR2 registers: In single scan mode only DMABADDR1 register must be 

configured with the base address of the display buffer in memory. In dual scan mode DMABADDR1 
should be configured with the base address of the Upper Panel display buffer and DMABADDR2 
should be configured with the base address of the Lower Panel display buffer.

– DMAFRMCFG register: Program the FRMSIZE field. Note that in dual scan mode the vertical size to 

use in the calculation is that of each panel. Respect to the BRSTLN field, a recommended value is a 4-
word burst.

– DMACON register: Once both the LCD Controller Core and the DMA Controller have been configured, 

enable the DMA Controller by writing a “1” to the DMAEN field of this register. If using a dual scan 
module or the 2D addressing feature, do not forget to write the DMAUPDT bit after every change to the 
set of DMA configuration values.

– DMA2DCFG register: Required only in 2D memory addressing mode (see 

).

• Finally, enable the LCD Controller Core by writing a “1” in the LCD_PWR field of the PWRCON register and do 

any other action that may be required to turn the LCD module on.

The double-buffer technique is used to avoid flickering while the frame being displayed is updated. Instead of using
a single buffer, there are two different buffers, the backbuffer (background buffer) and the primary buffer (the buffer
being displayed). 

The host updates the backbuffer while the LCD Controller is displaying the primary buffer. When the backbuffer
has been updated the host updates the DMA Base Address registers.

When using a Dual Panel LCD Module, both base address pointers should be updated in the same frame. There
are two possibilities:

• Check the DMAFRMPTx register to ensure that there is enough time to update the DMA Base Address 

registers before the end of frame.

• Update the Frame Base Address Registers when the End Of Frame IRQ is generated.

Once the host has updated the Frame Base Address Registers and the next DMA end of frame IRQ arrives, the
backbuffer and the primary buffer are swapped and the host can work with the new backbuffer.

When using a dual-panel LCD module, both base address pointers should be updated in the same frame. In order
to achieve this, the DMAUPDT bit in DMACON register must be used to validate the new base address.