Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 1070

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The LCDC can be configured to work on a frame buffer larger than the actual screen size. By changing the values
in a few registers, it is easy to move the displayed area along the frame buffer width and height.

Frame Buffer Addressing 

In order to locate the displayed window within a larger frame buffer, the software must:

• Program the DMABADDR1 (DMABADDR2) register(s) to make them point to the word containing the first pixel 

of the area of interest.

• Program the PIXELOFF field of DMA2DCFG register to specify the offset of this first pixel within the 32-bit 

memory word that contains it.

• Define the width of the complete frame buffer by programming in the field ADDRINC of DMA2DCFG register the 

address increment between the last word of a line and the first word of the next line (in number of 32-bit words).

• Enable the 2D addressing mode by writing the DMA2DEN bit in DMACON register. If this bit is not activated, the 

values in the DMA2DCFG register are not considered and the controller assumes that the displayed area 
occupies a continuous portion of the memory. 

The above configuration can be changed frame to frame, so the displayed window can be moved rapidly. Note that
the FRMSIZE field of DMAFRMCFG register must be updated with any movement of the displaying window. Note
also that the software must write bit DMAUPDT in DMACON register after each configuration for it to be accepted
by LCDC.

Note:

In 24 bpp packed mode, the DMA base address must point to a word containing a complete pixel (possible values of 
PIXELOFF are 0 and 8). This means that the horizontal origin of the displaying window must be a multiple of 4 pixels or 
a multiple of 4 pixels minus 1 (x = 4n or x = 4n-1, valid origins are pixel 0,3,4,7,8,11,12, etc.).

Displayed Image

Frame Buffer

Base word address &
pixel offset

Line-to-line 
address increment