Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 209

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal
driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate
(typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode
waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate
waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects.

 indicates the value of read and write parameters in slow clock mode.

 Read/write Cycles in Slow Clock Mode

A[

25:2]

NCS

1

MCK

NWE

1

1

NWE_CYCLE = 3

A

[25:2]

MCK

NRD

NRD_CYCLE = 2

1

1

NCS

SLOW CLOCK MODE WRITE

SLOW CLOCK MODE READ

NBS0, NBS1,
NBS2, NBS3,
A0,A1

NBS0, NBS1,
NBS2, NBS3,
A0,A1

 Read and Write Timing Parameters in Slow Clock Mode

NRD_SETUP

1

NWE_SETUP

1

NRD_PULSE

1

NWE_PULSE

1

NCS_RD_SETUP

0

NCS_WR_SETUP

0

NCS_RD_PULSE

2

NCS_WR_PULSE

3

NRD_CYCLE

2

NWE_CYCLE

3