Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
250
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
22.7
Programmable IO Delays
The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching
outputs on these busses may lead to a peak of current in the internal and external power supply lines.
outputs on these busses may lead to a peak of current in the internal and external power supply lines.
In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently
for pad buffers by means of configuration registers, DDRSDRC_DELAY1-8.
for pad buffers by means of configuration registers, DDRSDRC_DELAY1-8.
The additional programmable delays for each IO range from 0 to
4
ns (Worst Case PVT). The delay can differ
between IOs supporting this feature. Delay can be modified per programming for each IO. The minimal additional
delay that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay.
delay that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay.
When programming 0x0 in fields “Delay1 to Delay8”, no delay is added (reset value) and the propagation delay of
the pad buffers is the inherent delay of the pad buffer. When programming 0xF in field “Delay1” the propagation
delay of the corresponding pad is maximal.
the pad buffers is the inherent delay of the pad buffer. When programming 0xF in field “Delay1” the propagation
delay of the corresponding pad is maximal.
DDRSDRC_DELAY1, DDRSDRC_DELAY2 allow to configure delay on D[15:0], DDRSDRC_DELAY1[3:0] corre-
sponds to D[0] and DDRSDRC_DELAY2[3:0] corresponds to D[8].
sponds to D[0] and DDRSDRC_DELAY2[3:0] corresponds to D[8].
DDRSDRC_DELAY3, DDRSDRC_DELAY4 allow to configure delay on A13:0], DDRSDRC_DELAY3[3:0] corre-
sponds to A[0] and DDRSDRC_DELAY4[3:0] corresponds to A[8].
sponds to A[0] and DDRSDRC_DELAY4[3:0] corresponds to A[8].
Figure 22-26.
Programmable IO Delays
DELAY1
D[0]
Programmable Delay Line
SMC
D_out[0]
D_in[0]
DELAY2
D[1]
Programmable Delay Line
D_out[1]
D_in[1]
DELAYx
D[n]
Programmable Delay Line
D_out[n]
D_in[n]
A[m]
Programmable Delay Line
DELAYy
A[m]