Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 327

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The Main Oscillator is designed for a 12 MHz fundamental crystal. The 12 MHz is an input of the PLLA and the
UPLL used to generate the 480 MHz USB High Speed Clock (UPLLCK).

 shows the Main Oscillator block diagram.

Main Oscillator Block Diagram 

The typical crystal connection is illustrated in 

Figure 25-5

. For further details on the electrical characteristics of the

Main Oscillator, see the section “DC Characteristics” of the product datasheet.

Typical Crystal Connection

The startup time of the 12 MHz Main Oscillator is given in the section “DC Characteristics” of the product
datasheet.

To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is
selected.

The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCEN
bit in the Main Oscillator Register (CKGR_MOR). 

When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is
automatically cleared, indicating the main clock is off.

When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to
the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main
oscillator.

When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS
bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8

XIN

XOUT

Main Clock
MAINCK

PLLA and 

Divider

PLLA Clock
PLLACK

12M Main 

Oscillator

UPLL

UPLLCK

XIN

XOUT

GNDOSC