Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
329
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
25.8
UTMI Bias and Phase Lock Loop Programming
The multiplier is built-in to 40 to obtain the USB High Speed 480 MHz.
Whenever the UPLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically
cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UPLL counter. The UPLL
counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At this time, the LOCKU bit
is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock
cycles required to cover the UPLL transient time into the PLLCOUNT field. The BIAS, needed for High Speed oper-
ations, is enabled by writing BIASEN in CKGR_UCKR once the PLL locked.
cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UPLL counter. The UPLL
counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At this time, the LOCKU bit
is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock
cycles required to cover the UPLL transient time into the PLLCOUNT field. The BIAS, needed for High Speed oper-
ations, is enabled by writing BIASEN in CKGR_UCKR once the PLL locked.
UPLL
PLLCOUNT
LOCKU
UPLLEN
SLCK
MAINCK
UPLLCK
UPLL
Counter