Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
331
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 26-1.
SAM9M10 Power Management Controller Block Diagram
26.2.1
Main Application Modes
The Power Management Controller provides 3 main application modes.
26.2.1.1
Normal Mode
• PLLA and UPLL are running respectively at 400 MHz and 480 MHz
• USB Device High Speed and Host EHCI High Speed operations are allowed
• Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
• System Input clock is PLLACK, PCK is 400 MHz
• MDIV is ‘11’, MCK is 133 MHz
• DDR2 can be used at up to 133 MHz
26.2.1.2
USB HS and LP-DDR Mode
• Only UPLL is running at 480 MHz, PLLA power consumption is saved
• USB Device High Speed and Host EHCI High Speed operations are allowed
• Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
• System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz
• MDIV is ‘01’, MCK is 120 MHz
• Only LP-DDR can be used at up to 120 MHz
UHP48M
UHP12M
SysClk DDR
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,.../64
PCK
Processor
Clock
Controller
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
/1 /2 /3 /4
SLCK
MAINCK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
pck[..]
ON/OFF
UPLLCK
/1,/2
UPLLCK
USB
OHCI
USBDIV+1
/4
USB
EHCI
USBS
Divider
X /1 /1.5 /2