Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
373
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
27.7.3.8
SPI Direct Access Memory Controller (DMAC)
In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to reduce processor
overhead.
overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal
means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However,
changing the peripheral selection requires the Mode Register to be reprogrammed.
means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However,
changing the peripheral selection requires the Mode Register to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the
Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the periph-
eral it is destined to. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred
through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of
memory size for the buffers, but it provides a very effective means to exchange data with several peripherals with-
out any intervention of the processor.
Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the periph-
eral it is destined to. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred
through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of
memory size for the buffers, but it provides a very effective means to exchange data with several peripherals with-
out any intervention of the processor.
27.7.3.9
Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0
to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the
Mode Register (SPI_MR).
to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the
Mode Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e.,
one NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select
is driven low.
one NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select
is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either
the Mode Register or the Transmit Data Register (depending on PS).
the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing
any transfer, only 15 peripherals can be decoded.
any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select
defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the
externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make
sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the
externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make
sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This
is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line must be disabled.
This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.