Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation

During a transfer of more than one data on a Chip Select without the PDC

,

the

SPI_TDR is loaded by the

processor, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register.
When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the
end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the
Chip Select is not de-asserted between the two transfers. But depending on the application software handling the
SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor
may not reload the SPI_TDR in time to keep the chip select active (low). A null Delay Between Consecutive Trans-
fer (DLYBCT) value in the SPI_CSR register, will give even less time for the processor to reload the SPI_TDR.
With some SPI slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers
might lead to communication errors.

To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the
CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state
(low = active) until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select
will remain active. To have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER)
in the SPI_MR register must be set at 1 before writing the last data to transmit into the SPI_TDR.

When the Peripheral DMA Controller is used, the chip select line will remain low during the whole transfer since the
TDRE flag is managed by the PDC itself. The reloading of the SPI_TDR by the PDC is done as soon as TDRE flag
is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other PDC
channels connected to other peripherals are in use as well, the SPI PDC might be delayed by another (PDC with a
higher priority on the bus). Having PDC buffers in slower memories like flash memory or SDRAM compared to fast
internal SRAM, may lengthen the reload time of the SPI_TDR by the PDC as well. This means that the SPI_TDR
might not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between
data transfer and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT
bit might be needed. 

SPI Master

SPCK

MISO

MOSI

NPCS0

NPCS1

NPCS2

SPCK

1-of-n Decoder/Demultiplexer

MISO MOSI

NSS

Slave 0

SPCK MISO MOSI

NSS

Slave 1

SPCK MISO MOSI

NSS

Slave 14

NPCS3