Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The PIO interface consists of a series of signals driven by peripherals or directly by sofware. The simultaneous
switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. 

In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently
for pad buffers by means of configuration registers, PIO_DELAY.

For each I/O, the additional programmable delays range from 0 to 4 ns (Worst Case PVT). The delay can differ
between IOs supporting this feature. The delay can be modified according to programming for each I/O. The mini-
mum additional delay that can be programmed on a PAD supporting this feature is 1/16 of the maximum
programmable delay.

Only PADs PC[12], PC[7:2], PA[30:23] and PA[9:2] can be configured.

When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is
the inherent delay of the pad buffer. When programming 0xF in field, the propagation delay of the corresponding
pad is maximal.

Programmable I/O Delays

DELAY1

Programmable Delay Line

PIO

PAout[0]

PAin[0]

DELAY2

Programmable Delay Line

DELAYx

Programmable Delay Line

PAout[1]

PAin[1]

PAout[2]

PAin[2]