Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 500

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART
behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The
difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is con-
trolled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in 

.

Typical Connection to a RS485 Bus 

The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the
value 0x1. 

The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is
programmed so that the line can remain driven after the last character completion. 

 gives an example

of the RTS waveform during a character transmission when the timeguard is enabled.

Example of RTS Drive with Timeguard

The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with
external devices in Master or Slave Mode. It also enables communication between processors if an external pro-
cessor is connected to the system.

The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as
“slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one
master may simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Mas-

USART

RTS

TXD

RXD

Differential 

Bus

D0

D1

D2

D3

D4

D5

D6

D7

TXD

Start 

Bit

Parity

Bit

Stop

Bit

Baud Rate

 Clock

TG = 4

Write

US_THR

TXRDY

TXEMPTY

RTS