Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 502

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

• to obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at 

least 4 times lower than the system clock.

Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.

The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). The 9
bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in
SPI Mode (Master or Slave). 

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters deter-
mine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two
possible states, resulting in four possible combinations that are incompatible with one another. Thus, a mas-
ter/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in
different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.

SPI Bus Protocol Mode

0

0

1

1

0

0

2

1

1

3

1

0