Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
1113
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
46.15.1 Power-Up Sequence
Figure 46-6. V
DDCORE
and V
DDIO
Constraints at Startup
V
DDCORE
and V
DDBU
are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach their
target values prior to the release of POR.
V
DDIOP
must be
≥ V
IH
(refer to DC characteristics,
, for more details), (t
res
+ t
1
) at the latest, after V
DDCORE
has reached
V
th+
.
V
DDIOM
must reach V
OH
(refer to DC characteristics,
, for more details), (t
res
+ t
1
+ t
2
) at the latest, after
V
DDCORE
has reached
V
th+
t
RES
is a POR characteristic
t
1
= 3
× t
SLCK
t
2
= 16
× t
SLCK
The t
SLCK
min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz).
t
RES
= 30 µs
t
1
= 66 µs
t
2
= 352 µs
V
DDPLL
is to be established prior to V
DDCORE
to ensure the PLL is powered once enabled into the ROM code.
As a conclusion, establish V
DDIOP
and V
DDIOM
first, then V
DDPLL
, and V
DDCORE
last, to ensure a reliable operation of the
device.
V
DD
(V)
Core Supply POR Output
VDDIOtyp
V
IH
V
th+
t
SLCK
t
res
V
DDIO
> V
IH
V
DDCORE
V
DDIO
t
1
VDDCOREtyp
V
OH
V
DDIO
> V
OH
t
2