Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
1114
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
46.16 SMC Timings
46.16.1 Timing Conditions
SMC Timings are given for Max corners.
Timings are given assuming a capacitance load on data, control and address pads.
In the following tables, t
CPMCK
is MCK period.
46.16.2 Timing Extraction
46.16.2.1 Zero Hold Mode Restrictions
Table 46-30. Capacitance Load
Supply
Corner
Max
Min
3.3V
50 pF
5 pF
1.8V
30 pF
5 pF
Table 46-31. Zero Hold Mode Use Maximum System Clock Frequency (MCK)
Symbol
Parameter
Max
Unit
VDDIOM supply 1.8V
VDDIOM supply 3.3V
f
max
MCK frequency
66
66
MHz